GMS30C2116 Datasheet, PDF (240/322 Pages) Hynix Semiconductor – USERS MANUAL

A-66
Delayed Branch
Appendix A. Instruction Set Details
DBR
Format:
PCrel format
15
87 6
0
OP-code
0
low-rel
S
1110 1100
S: sign bit of rel
rel = 25 S // low-rel // 0
range -128 ~ 126
Notation:
DBR rel
Description:
Place the branch address PC + rel (relative of the first byte after the Branch instruction) in
the program counter PC. All condition flags and the cache mode flag M remain unchanged.
Then the instruction after the Delayed Branch instruction, called the delay instruction, is
executed regardless of whether the delayed branch is taken or not taken
Operation:
PC := PC + rel
Exceptions:
None.