GMS30C2116 Datasheet, PDF (56/322 Pages) Hynix Semiconductor – USERS MANUAL

2-8
CHAPTER 2
2.4 Entry Tables
Spacing of the entries for the Trap instructions and exceptions is four bytes. These entries
are intended to each contain an instruction branching to the associated function. The entries
for the TRAPxx instructions are the same as for TRAP. Table 2.6 shows the trap entries
when the entry table is mapped to the end of memory area MEM3 (default after Reset):
Address (Hex) Entry Description
FFFF FF00 TRAP 0
FFFF FF04 TRAP 1
:
:
FFFF FFC0 TRAP 48 IO2 Interrupt
-- priority 15
FFFF FFC4 TRAP 49 IO1 Interrupt
-- priority 14
FFFF FFC8 TRAP 50 INT4 Interrupt
-- priority 13
FFFF FFCC TRAP 51 INT3 Interrupt
-- priority 11
FFFF FFD0 TRAP 52 INT2 Interrupt
-- priority 9
FFFF FFD4 TRAP 53 INT1 Interrupt
-- priority 7
FFFF FFD8 TRAP 54 IO3 Interrupt
-- priority 5
FFFF FFDC TRAP 55 Timer Interrupt
-- priority selectable as 6, 8, 10, 12
FFFF FFE0 TRAP 56 Reserved
-- priority 17 (lowest)
FFFF FFE4 TRAP 57 Trace Exception
-- priority 16
FFFF FFE8 TRAP 58 Parity Error
-- priority 4
FFFF FFEC TRAP 59 Extended Overflow
-- priority 3
FFFF FFF0 TRAP 60 Range, Pointer, Frame and Privilege Error
-- priority 2
FFFF FFF4 TRAP 61 Reserved
-- priority 1
FFFF FFF8 TRAP 62 Reset
-- priority 0 (highest)
FFFF FFFC TRAP 63 Error entry for instruction code of all ones
Table 2.6: Trap entry table mapped to the end of MEM3