GMS30C2116 Datasheet, PDF (152/322 Pages) Hynix Semiconductor – USERS MANUAL

6-30
6.11.2 DRAM RAS Access
Address Bus
(high order bits)
WE#
Address Bus
(low order bits)
undefined
row address
t₁
t₂
column address
RAS#
t₃
t₄
CAS0#..CAS3#
Figure 6.11: DRAM RAS Access
CHAPTER 6
Symbol Description
Formula
t₁ Row Address A12..A0 setup time (number of RAS precharge cycles - 1) x t_CLK
to RAS# (min.)
+ t_CLKWH + 0.5 ns + ∆t_N (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signal RAS#
(b) refers to capacitive load on signals A12..A0
t₂ Row Address A12..A0 hold time (number of RAS to CAS delay cycles -1) x t_CLK
after RAS# (min.)
+ t_CLKWL - 1.1 ns + ∆t_P (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals A12..A0
(b) refers to capacitive load on signal RAS#
t₃ RAS# pulse width high
(RAS# precharge) (min.)
(number of RAS precharge cycles) x t_CLK
t₄ RAS# low before end of
CAS0#..CAS3# (min.)
(number of RAS to CAS delay cycles
+ access cycles - 1) x t_CLK
+ t_CLKWL - 2.5 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signal RAS#