GMS30C2116 Datasheet, PDF (159/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-37
6.11.5.2 Single-Cycle Access
Symbol Description
Formula
t_1a A25..A13, CS0#..CS3# setup
(number of setup cycles) x t_CLK + t_CLKWH
time to WE0#..WE3#, OE# (min.) _{- 4.1 ns + ∆tP (a) - ∆tN (b)}
t_1b A12..A0 setup time to
WE0#..WE3#, OE# (min.)
(number of setup cycles) x t_CLK + t_CLKWH
- 3.2 ns + ∆t_P (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals WE0#..WE3#,
OE#
(b) refers to capacitive load on signals A25..A0,
CS0#..CS3#
t_2a A25..A13, CS0#..CS3# valid
(number of setup cycles + 1) x t_CLK
before end of WE0#..WE3#, OE#
(min.)
- 2.6 ns + ∆t_P (a) - ∆t_N (b)
t_2b A12..A0 valid before end of
WE0#..WE3#, OE# (min.)
(number of setup cycles + 1) x t_CLK
-1.7 ns + ∆t_P (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals WE0#..WE3#,
OE#
(b) refers to capacitive load on signals A25..A0,
CS0#..CS3#
t₃ D31..D0, DP0..DP3 valid before (number of setup cycles + 1) x t_CLK
end of WE0#...WE3# (min.)
- 2.8 ns + ∆t_P (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals WE0#..WE3#
(b) refers to capacitive load on signals D31..D0,
DP0..DP3
t₄ WE0#..WE3#, OE# pulse width t_CLKWL + 0.5 ns
low (min.)
t_5a A25..A13, CS0#..CS3# hold time (number of bus hold cycles) x t_CLK
after WE0#..WE3#, OE# (min.) _{+ 1.1 ns + ∆tN (a) - ∆tP (b)}
t_5b A12..A0 hold time after
WE0#..WE3#, OE# (min.)
(number of bus hold cycles) x t_CLK
+ 0.7 ns + ∆t_P (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals A25..A0,
CS0#..CS3#
(b) refers to capacitive load on signals WE0#..WE3#,
OE#
t₆ D31..D0, DP0..DP3 hold time (number of bus hold cycles) x t_CLK
after WE0#..WE3# (min.)
+ 1.2 ns + ∆t_N (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals D31..D0,
DP0..DP3
(b) refers to capacitive load on signals WE0#...WE3#