GMS30C2116 Datasheet, PDF (299/322 Pages) Hynix Semiconductor – USERS MANUAL

Appendix A. Instruction Set Details
Set Conditional Instruction
A-125
SETxx
Format:
Rn format
15
OP-code
1011 10
7
43
0
dn
Rd-code
n
d = 0: Rd-code encodes G0..G15 for Rd
d = 1: Rd-code encodes L0..L15 for Rd
n: Bit 8 // bits 3..0 encode n = 0..31
Notation:
SETxx Rd
Description:
The destination register is set or cleared according to the states of the condition flags
specified by n. The condition flags themselves remain unchanged.
The Set Conditional instruction share the basic OP-code SETxx, they are differentiated by
n = 1..31 and not denoting the SR or the PC.
l n = 0 while not denoting the SR or the PC differentiates the Set Stack Address
instruction.
l n = 1..31 while not denoting the SR or the PC differentiates the Set Conditional
instruction.
l Denoting the SR differentiates the Fetch instruction.
l Denoting the PC is reserved for future use.
Operation:
n Notation or
1 Reserved
2 SET1 Rd
3 SET0 Rd
4 SETLE Rd
5 SETGT Rd
6 SETLT Rd
7 SETGE Rd
8 SETSE Rd
9 SETHT Rd
10 SETST Rd
Alternative
SETN Rd
SETNN Rd
SETC Rd
Operation
Rd := 1;
Rd := 0;
if N = 1 or Z = 1 then Rd := 1 else Rd := 0;
if N = 0 and Z = 0 then Rd := 1 else Rd := 0;
if N = 1 then Rd := 1 else Rd := 0;
if N = 0 then Rd := 1 else Rd := 0;
if C = 1 or Z = 1 then Rd := 1 else Rd := 0;
if C = 0 and Z = 0 then Rd := 1 else Rd := 0;
if C = 1 then Rd := 1 else Rd := 0;