GMS30C2116 Datasheet, PDF (136/322 Pages) Hynix Semiconductor – USERS MANUAL

6-14
6.4 Memory Control Register MCR (continued)
Bits Name
7..6 MEM3BusSize
5..4 MEM2BusSize
3..2 MEM1BusSize
1..0 MEM0BusSize
Description
11 = 8 bit
10 = 16 bit
01 = reserved
00 = 32 bit
11 = 8 bit
10 = 16 bit
01 = reserved
00 = 32 bit
11 = 8 bit
10 = 16 bit
01 = reserved
00 = 32 bit
11 = 8 bit
10 = 16 bit
01 = reserved
00 = 32 bit
Table 6.4: Memory Control Register MCR
CHAPTER 6
6.4.1 Output Voltage
Bit 25 of the MCR controls the voltage of the output signals. The default setting is rail-to
rail. At a supply voltage of 5V, MCR(25) must be cleared to reduce the high-output signal
in order to save on switching power consumption.
6.4.2 Input Threshold
Bit 24 of the MCR controls the input threshold voltage. The default setting is for a supply
voltage of 5V. MCR(24) must be cleared for a supply voltage of 3.3V.
6.4.3 Power Down
Bit 22 of the MCR controls the power-down mode. The default setting is processor active.
To switch the processor to power-down mode MCR(22) must be cleared. The switch to
power-down is initiated by a transition from MCR(22) = 1 to MCR(22) = 0; thus,
MCR(22) must be restored to one for at least one cycle before a new switch to power-down
mode can occur.
In power-down mode, only the logic for the timer, IO3Control modes, interrupt and refresh
is being clocked, all other clocks are disabled. The switch to power-down mode is delayed
until the memory pipeline is empty. The processor is activated temporarily for refresh and
bus arbitration cycles and is switched back to processor active by any interrupt or on Reset.
Note that MCR(22) is not switched back to one by an interrupt.