GMS30C2116 Datasheet, PDF (124/322 Pages) Hynix Semiconductor – USERS MANUAL

6-2
6.1.1.1 SRAM and ROM Single-Cycle Read Access
CLK
CHAPTER 6
Chip Select
Address Bus
addr. 1
addr. 2
addr. 3
addr. 4
addr. 5
WE0#..WE3#
OE#
Data Bus
(read data)
data 1
data 2
data 3
data 4
data 5
Figure 6.1: SRAM and ROM Single-Cycle Read Access
6.1.1.2 SRAM and ROM Multi-Cycle Read Access
CLK
Chip Select
Address Bus
WE0#..WE3#
OE#
Data Bus
Address
setup time
0..1 cycles
Access time
2..16 cycles
Figure 6.2: SRAM and ROM Multi-Cycle Read Access
Bus hold
time
0..7 cycles