MC9S12KG128_10 Datasheet, PDF (95/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

All bits read 0 and are not writable.
Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
2.3.2.15 RESERVED5
This register is reserved for factory testing and is not accessible.
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-22. RESERVED5
All bits read 0 and are not writable.
2.4 Functional Description
2.4.1 Flash Command Operations
Write and read operations are both used for the program, erase, erase verify, and data compress algorithms
described in this subsection. The program and erase algorithms are time controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO)
so that a second command along with the necessary data and address can be stored to the buffer while the
first command remains in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with interrupts generated, if enabled.
The next paragraphs describe:
1. How to write the FCLKDIV register.
2. Command write sequences used to program, erase, and verify the Flash memory.
3. Valid Flash commands.
4. Effects resulting from illegal Flash command write sequences or aborting Flash operations.
2.4.1.1 Writing the FCLKDIV Register
Prior to issuing any program, erase, erase verify, or data compress command, it is first necessary to write
the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range.
Because the program and erase timings are also a function of the bus clock, the FCLKDIV determination
must take this information into account.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
95