MC9S12KG128_10 Datasheet, PDF (187/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4) Block Description
Table 5-4. CLKSEL Field Descriptions (continued)
Field
Description
2
CWAI
1
RTIWAI
0
COPWAI
Core Stops in Wait Mode Bit — Write: anytime
0 Core clock keeps running in wait mode.
1 Core clock stops in wait mode.
RTI Stops in Wait Mode Bit — Write: anytime
0 RTI keeps running in wait mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime
0 COP keeps running in wait mode.
1 COP stops and initializes the COP dividers whenever the part goes into wait mode.
5.3.2.7 CRG PLL Control Register (PLLCTL)
This register controls the PLL functionality.
Module Base + 0x0006
R
W
Reset
7
CME
1
6
5
4
3
2
0
PLLON
AUTO
ACQ
PRE
1
1
1
0
0
= Unimplemented or Reserved
Figure 5-10. CRG PLL Control Register (PLLCTL)
Read: anytime
Write: refer to each bit for individual write conditions
Table 5-5. PLLCTL Field Descriptions
1
PCE
0
0
SCME
1
Field
7
CME
6
PLLON
Description
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock
mode.
Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause
unpredictable operation of the MCU.
Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss
of clock will not be detected.
Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the
PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.
0 PLL is turned off.
1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
187