MC9S12KG128_10 Datasheet, PDF(444/606 Page) Freescale Semiconductor, Inc – HCS12 Microcontrollers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC9S12KG128_10 Datasheet, PDF (444/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

◁

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description

14.2.3 VDD, VSS â Regulator Output1 (Core Logic)

Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core

logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF,

X7R ceramic).

In shutdown mode an external supply at VDD/VSS can replace the voltage regulator.

14.2.4 VDDPLL, VSSPLL â Regulator Output2 (PLL)

Signals VDDPLL/VSSPLL are the secondary outputs of VREG3V3V2 that provide the power supply for the

PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors

(100 nF...220 nF, X7R ceramic).

In shutdown mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator.

14.2.5 VREGEN â Optional Regulator Enable

This optional signal is used to shutdown VREG3V3V2. In that case VDD/VSS and VDDPLL/VSSPLL must

be provided externally. shutdown mode is entered with VREGEN being low. If VREGEN is high, the

VREG3V3V2 is either in full-performance mode or in reduced-power mode.

For the connectivity of VREGEN see device overview chapter.

NOTE

Switching from FPM or RPM to shutdown of VREG3V3V2 and vice versa

is not supported while the MCU is powered.

14.3 Memory Map and Register Deï¬nition

This subsection provides a detailed description of all registers accessible in VREG3V3V2.

14.3.1 Module Memory Map

Figure 14-2 provides an overview of all used registers.

Table 14-2. VREG3V3V2 Memory Map

Address

Offset

0x0000

Use

VREG3V3V2 Control Register (VREGCTRL)

Access

R/W

MC9S12KG128 Data Sheet, Rev. 1.16

444

Freescale Semiconductor

▷