MC9S12KG128_10 Datasheet, PDF (265/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

MSB
LSB
SCL
1 2 34 5 6 78 9
Chapter 8 Inter-Integrated Circuit (IICV2) Block Description
MSB
LSB
1 2 34 5 6 78 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX D7 D6 D5 D4 D3 D2 D1 D0
Start
Signal
Calling Address
Read/ Ack
Write ^Bit
MSB
LSB
SCL
1 2 34 5 67 89
Data Byte
No Stop
Ack Signal
Bit
MSB
LSB
1 234 5 678 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
Read/ Ack
Write ^Bit
Repeated
Start
Signal
New Calling Address
Read/ No Stop
Write
Ack Signal
Bit
Figure 8-9. IIC-Bus Transmission Signals
8.4.1.1 START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in Figure 8-9, a START
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
SDA
SCL
START Condition
STOP Condition
Figure 8-10. Start and Stop Conditions
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
265