MC9S12KG128_10 Datasheet, PDF (331/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 10 Serial Communications Interface (S12SCIV2) Block Description
• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
• If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
10.1.3.3 Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
10.1.4 Block Diagram
Figure 10-1 is a high level block diagram of the SCI module, showing the interaction of various functional
blocks.
RX DATA IN
BUS CLOCK
SCI DATA REGISTER
RECEIVE SHIFT REGISTER
RECEIVE & WAKE UP CONTROL
BAUD
GENERATOR
÷16
DATA FORMAT CONTROL
TRANSMIT CONTROL
TRANSMIT SHIFT REGISTER
SCI DATA REGISTER
IDLE IRQ
RDR/OR IRQ
TDRE IRQ
TC IRQ
IRQ
TO CPU
Figure 10-1. SCI Block Diagram
TXDATA OUT
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
331