MC9S12KG128_10 Datasheet, PDF (203/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4) Block Description
Table 5-11. Outcome of Clock Loss in Wait Mode
CME
0
1
1
SCME
X
0
1
SCMIE
CRG Actions
X Clock failure -->
No action, clock loss not detected.
X Clock failure -->
CRG performs Clock Monitor Reset immediately
0 Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting Wait Mode.
– MCU remains in Wait Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
– SCM deactivated,
– PLL disabled depending on PLLWAI,
– VREG remains enabled (never gets disabled in Wait Mode).
– MCU remains in Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit Wait Mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
or an External Reset is applied.
– Exit Wait Mode using OSCCLK as system clock,
– Start reset sequence.
Scenario 2: OSCCLK does not recover prior to exiting Wait Mode.
– MCU remains in Wait Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag,
– Keep performing Clock Quality Checks (could continue infinitely)
while in Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit Wait Mode in SCM using PLL clock (f_SCM) as system clock,
– Continue to perform additional Clock Quality Checks until OSCCLK
is o.k. again.
or an External RESET is applied.
– Exit Wait Mode in SCM using PLL clock (f_SCM) as system clock,
– Start reset sequence,
– Continue to perform additional Clock Quality Checks until OSCCLK
is o.k.again.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
203