MC9S12KG128_10 Datasheet, PDF (464/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Background Debug Module (BDMV4) Block Description
clock cycle earlier. Synchronization between the host and target is established in this manner at the start
of every bit time.
Figure 15-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally
driven signals.
CLOCK
TARGET SYSTEM
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START OF BIT TIME
TARGET SENSES BIT
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
Figure 15-7. BDM Host-to-Target Serial Bit Timing
EARLIEST
START OF
NEXT BIT
The receive cases are more complicated. Figure 15-8 shows the host receiving a logic 1 from the target
system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
MC9S12KG128 Data Sheet, Rev. 1.16
464
Freescale Semiconductor