MC9S12KG128_10 Datasheet, PDF (161/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.4.6
Chapter 4 Port Integration Module (PIM9KG128V1)
Port P Polarity Select Register (PPSP)
Module Base + 0x001D
7
R
PPSP7
W
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
1
PPSP1
0
PPSP0
Reset
0
0
0
0
0
0
0
0
Figure 4-28. Port P Polarity Select Register (PPSP)
Read: Anytime. Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
Table 4-27. PPSP Field Descriptions
Field
Description
7–0
PPSP[7:0]
Polarity Select Port P
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
4.3.4.7 Port P Interrupt Enable Register (PIEP)
Module Base + 0x001E
7
R
PIEP7
W
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
Reset
0
0
0
0
0
0
Figure 4-29. Port P Interrupt Enable Register (PIEP)
Read: Anytime. Write: Anytime.
1
PIEP1
0
0
PIEP0
0
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port P.
Table 4-28. PIEP Field Descriptions
Field
Description
7–0
PIEP[7:0]
Interrupt Enable Port P
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
161