MC9S12KG128_10 Datasheet, PDF (155/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.3.7 Port M Wired-OR Mode Register (WOMM)
Module Base + 0x0016
R
W
Reset
7
WOMM7
0
6
WOMM6
0
5
WOMM5
0
4
WOMM4
0
3
WOMM3
0
2
WOMM2
0
Figure 4-21. Port M Wired-OR Mode Register (WOMM)
Read: Anytime. Write: Anytime.
1
WOMM1
0
0
WOMM0
0
This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the CAN outputs and allows a multipoint
connection of several serial modules. This bit has no influence on pins used as inputs.
Table 4-16. WOMM Field Descriptions
Field
Description
7–0
Wired-OR Mode Port M
WOMM[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
4.3.3.8 Module Routing Register (MODRR)
Module Base + 0x0017
7
R
0
W
6
MODRR6
5
MODRR5
4
MODRR4
3
MODRR3
2
MODRR2
1
MODRR1
0
MODRR0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-22. Module Routing Register (MODRR)
Read: Anytime. Write: Anytime.
This register configures the re-routing of CAN0, CAN4, SPI0, SPI1 and SPI2 on defined port pins.
Table 4-17. MODRR Field Descriptions
Field
6
MODRR6
5
MODRR5
4
MODRR4
SPI2 Routing Bit — See Table 4-22.
SPI1 Routing Bit — See Table 4-21.
SPI0 Routing Bit — See Table 4-20.
Description
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
155