MC9S12KG128_10 Datasheet, PDF (162/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.4.8 Port P Interrupt Flag Register (PIFP)
Module Base + 0x001F
7
R
PIFP7
W
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
1
PIFP1
0
PIFP0
Reset
0
0
0
0
0
0
0
0
Figure 4-30. Port P Interrupt Flag Register (PIFP)
Read: Anytime. Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSP register. To clear this flag, write “1” to the corresponding bit in the PIFP register.
Writing a “0” has no effect.
Table 4-29. Field Descriptions
Field
Description
7–0
PIFP[7:0]
Interrupt Flags Port P
0 No active edge pending.
Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
MC9S12KG128 Data Sheet, Rev. 1.16
162
Freescale Semiconductor