MC9S12KG128_10 Datasheet, PDF (256/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 8 Inter-Integrated Circuit (IICV2) Block Description
SDA
SCL
SCL Hold(start)
SCL Hold(stop)
START condition
STOP condition
Figure 8-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 8-5. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
IBC[7:0]
(hex)
MUL=1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
Table 8-5. IIC Divider and Hold Values (Sheet 1 of 5)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
20
7
6
22
7
7
24
8
8
26
8
9
28
9
10
30
9
11
34
10
13
40
10
16
28
7
10
32
7
12
36
9
14
40
9
16
44
11
18
48
11
20
56
13
24
68
13
30
48
9
18
SCL Hold
(stop)
11
12
13
14
15
16
18
21
15
17
19
21
23
25
29
35
25
MC9S12KG128 Data Sheet, Rev. 1.16
256
Freescale Semiconductor