MC9S12KG128_10 Datasheet, PDF (557/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 19 Module Mapping Control (MMCV4) Block Description
19.3.2.9 Program Page Index Register (PPAGE)
Module Base + 0x0030
Starting address location affected by INITRG register setting.
7
R
0
W
Reset¹
—
6
5
4
3
2
1
0
0
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
—
—
—
—
—
—
—
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
actual reset state of this register.
= Unimplemented or Reserved
Read: Anytime
Figure 19-11. Program Page Index Register (PPAGE)
Write: Determined at chip integration. Generally it’s: “write anytime in all modes;” on some devices it will
be: “write only in special modes.” Check specific device documentation to determine which applies.
Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with
write only in special modes), see device overview chapter.
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page
index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six
page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF
as defined in Table 19-14. CALL and RTC instructions have special access to read and write this register
without using the address bus.
NOTE
Normal writes to this register take one cycle to go into effect. Writes to this
register using the special access of the CALL and RTC instructions will be
complete before the end of the associated instruction.
Table 19-13. MEMSIZ0 Field Descriptions
Field
5:0
PIX[5:0]
Description
Program Page Index Bits 5:0 — These page index bits are used to select which of the 64 FLASH or ROM
array pages is to be accessed in the program page window as shown in Table 19-14.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
557