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MC9S12KG128_10 Datasheet, PDF (293/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers | |||
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Chapter 9 Freescaleâs Scalable Controller Area Network (S12MSCANV2)
9.3.2.12 MSCAN Identiï¬er Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identiï¬er acceptance control as described below.
Module Base + 0x000B
R
W
Reset:
7
6
5
4
3
2
1
0
0
0
IDHIT2
IDHIT1
IDAM1
IDAM0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-15. MSCAN Identiï¬er Acceptance Control Register (CANIDAC)
0
IDHIT0
0
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are
read-only
Table 9-16. CANIDAC Register Field Descriptions
Field
Description
5:4
IDAM[1:0]
2:0
IDHIT[2:0]
Identiï¬er Acceptance Mode â The CPU sets these ï¬ags to deï¬ne the identiï¬er acceptance ï¬lter organization
(see Section 9.4.3, âIdentiï¬er Acceptance Filterâ). Table 9-17 summarizes the different settings. In ï¬lter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
Identiï¬er Acceptance Hit Indicator â The MSCAN sets these ï¬ags to indicate an identiï¬er acceptance hit (see
Section 9.4.3, âIdentiï¬er Acceptance Filterâ). Table 9-18 summarizes the different settings.
IDAM1
0
0
1
1
IDHIT2
0
0
0
0
1
1
1
1
Table 9-17. Identiï¬er Acceptance Mode Settings
IDAM0
0
1
0
1
Identiï¬er Acceptance Mode
Two 32-bit acceptance ï¬lters
Four 16-bit acceptance ï¬lters
Eight 8-bit acceptance ï¬lters
Filter closed
Table 9-18. Identiï¬er Acceptance Hit Indication
IDHIT1
0
0
1
1
0
0
1
1
IDHIT0
0
1
0
1
0
1
0
1
Identiï¬er Acceptance Hit
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
Filter 4 hit
Filter 5 hit
Filter 6 hit
Filter 7 hit
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
293
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