MC9S12KG128_10 Datasheet, PDF (197/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4) Block Description
check window
VCO
clock
12 3
49999 50000
OSCCLK
12345
4096
4095
osc ok
Figure 5-19. Check Window Example
The sequence for clock quality check is shown in Figure 5-20.
Clock OK
CM fail
POR LVR
exit full stop
Clock Monitor Reset
num=0
check window
osc ok
no
?
yes
Enter SCM
yes
num=num+1
yes
num<50
no
?
no
SCM
active?
yes
SCME=1
no
?
num=50
SCM
active?
no
yes
Switch to OSCCLK
Exit SCM
Figure 5-20. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by self-clock mode
or clock monitor reset¹ handling the clock quality checker continues to
check the OSCCLK signal.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
197