MC9S12KG128_10 Datasheet, PDF (254/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 8 Inter-Integrated Circuit (IICV2) Block Description
Table 8-1. IBAD Field Descriptions
Field
Description
7:1
ADR[7:1]
0
Reserved
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
8.3.2.2 IIC Frequency Divider Register (IBFD)
Offset Module Base + 0x0001
R
W
Reset
7
IBC7
0
6
IBC6
5
IBC5
4
IBC4
3
IBC3
2
IBC2
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-4. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
Table 8-2. IBFD Field Descriptions
1
IBC1
0
0
IBC0
0
Field
7:0
IBC[7:0]
Description
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 8-3.
IBC5-3
(bin)
000
001
Table 8-3. I-Bus Tap and Prescale Values
IBC2-0
(bin)
000
001
010
011
100
101
110
111
SCL Tap
(clocks)
5
6
7
8
9
10
12
15
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
scl2start
(clocks)
2
2
scl2stop
(clocks)
7
7
scl2tap
(clocks)
4
4
tap2tap
(clocks)
1
2
MC9S12KG128 Data Sheet, Rev. 1.16
254
Freescale Semiconductor