MC9S12KG128_10 Datasheet, PDF (333/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 10 Serial Communications Interface (S12SCIV2) Block Description
10.3 Memory Map and Registers
This section provides a detailed description of all memory and registers.
10.3.1 Module Memory Map
The memory map for the SCI module is given below in Figure 10-2. The Address listed for each register
is the address offset. The total address for each register is the sum of the base address for the SCI module
and the address offset for each register.
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
Name
SCIBDH
SCIBDL
SCICR1
SCICR2
SCISR1
SCISR2
SCIDRH
SCIDRL
Bit 7
R
0
W
R
SBR7
W
R
LOOPS
W
R
TIE
W
R TDRE
W
R
0
W
R R8
W
R R7
W T7
6
0
SBR6
SCISWAI
TCIE
TC
0
T8
R6
T6
5
0
SBR5
RSRC
RIE
RDRF
0
0
R5
T5
4
SBR12
SBR4
M
ILIE
IDLE
0
0
R4
T4
3
SBR11
SBR3
WAKE
TE
OR
0
0
R3
T3
= Unimplemented or Reserved
Figure 10-2. SCI Register Summary
2
SBR10
SBR2
ILT
RE
NF
BRK13
0
R2
T2
1
SBR9
SBR1
PE
RWU
FE
TXDIR
0
R1
T1
Bit 0
SBR8
SBR0
PT
SBK
PF
RAF
0
R0
T0
10.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register location do not have any effect and
reads of these locations return a zero. Details of register bit and field function follow the register diagrams,
in bit order.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
333