MC9S12KG128_10 Datasheet, PDF (24/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1)
1.2.1 Signal Properties Summary
Table 1-2 summarizes the pin functionality. Signals shown in bold are not available in the 80-pin package.
Table 1-3 summarizes the power and ground pins.
Table 1-2. Signal Properties (Sheet 1 of 3)
Pin Name
Function 1
EXTAL
XTAL
RESET
TEST
VREGEN
XFC
BKGD
PAD[15:8]
PAD[7:0]
PA[7:0]
PB[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
Pin Name
Function 2
—
—
—
—
—
—
TAGHI
AN[15:8]
AN[7:0]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
NOACC
IPIPE1
IPIPE0
ECLK
LSTRB
R/W
IRQ
XIRQ
KWH7
KWH6
KWH5
Pin Name Pin Name Powered
Function 3 Function 4 by
Internal Pull
Resistor
CTRL
Reset
State
Description
—
—
VDDPLL
NA
NA Oscillator Pins
—
—
VDDPLL
NA
NA
—
—
VDDR
None
None External Reset
—
—
NA
NA
NA Test Input
—
—
VDDX
NA
NA Voltage Regulator Enable Input
—
—
VDDPLL
NA
NA PLL Loop Filter
MODC
—
—
—
—
VDDR Always Up Up Background Debug, Tag High,
Mode Input
—
VDDA
None
None Port AD Input, Analog Inputs of
ATD
—
VDDA
None
None Port AD Input, Analog Inputs of
ATD
—
VDDR PUCR Disabled Port A I/O, Multiplexed
Address/Data
—
XCLKS
—
VDDR PUCR Disabled Port B I/O, Multiplexed
Address/Data
—
VDDR PUCR
Up Port E I/O, Access, Clock Select
MODB
MODA
—
—
VDDR
While RESET Port E I/O, Pipe Status, Mode
pin is low:
Input
Down
—
VDDR
While RESET Port E I/O, Pipe Status, Mode
pin is low:
Input
Down
—
VDDR PUCR
Up Port E I/O, Bus Clock Output
TAGLO
—
—
VDDR PUCR
Up Port E I/O, Byte Strobe, Tag Low
—
VDDR PUCR
Up Port E I/O, R/W in expanded
modes
—
—
VDDR PUCR
Up Port E Input, Maskable Interrupt
—
—
VDDR PUCR
Up Port E Input, Non Maskable
Interrupt
SS2
—
VDDR PERH/ Disabled Port H I/O, Interrupt, SS of SPI2
PPSH
SCK2
MOSI2
—
VDDR PERH/ Disabled Port H I/O, Interrupt, SCK of
PPSH
SPI2
—
VDDR PERH/ Disabled Port H I/O, Interrupt, MOSI of
PPSH
SPI2
MC9S12KG128 Data Sheet, Rev. 1.16
24
Freescale Semiconductor