MC9S12KG128_10 Datasheet, PDF (379/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 11 Serial Peripheral Interface (SPIV3) Block Description
11.5 Reset
The reset values of registers and signals are described in the Memory Map and Registers section (see
Section 11.3, “Memory Map and Register Definition”) which details the registers and their bit-fields.
• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the byte last received from the master before the reset.
• Reading from the SPIDR after reset will always read a byte of zeros.
11.6 Interrupts
The SPIV3 only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following
is a description of how the SPIV3 makes a request and how the MCU should acknowledge that request.
The interrupt vector offset and interrupt priority are chip dependent.
The interrupt flags MODF, SPIF and SPTEF are logically ORed to generate an interrupt request.
11.6.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see Table 11-3). After MODF is set, the current transfer is aborted and the following bit is
changed:
• MSTR = 0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in Section 11.3.2.4, “SPI Status Register (SPISR).”
11.6.2 SPIF
SPIF occurs when new data has been received and copied to the SPI Data Register. After SPIF is set, it
does not clear until it is serviced. SPIF has an automatic clearing process which is described in
Section 11.3.2.4, “SPI Status Register (SPISR).” In the event that the SPIF is not serviced before the end
of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be
ignored and no new data will be copied into the SPIDR.
11.6.3 SPTEF
SPTEF occurs when the SPI Data Register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process which is described in Section 11.3.2.4, “SPI
Status Register (SPISR).”
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
379