MC9S12KG128_10 Datasheet, PDF (483/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 16 Debug Module (DBGV1) Block Description
Table 16-3. DBGC1 Field Descriptions (continued)
Field
Description
4
BEGIN
3
DBGBRK
1:0
CAPMOD
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace
buffer. See Section 16.4.2.8.1, “Storing with Begin-Trigger,” and Section 16.4.2.8.2, “Storing with End-Trigger,”
for more details.
0 Trigger at end of stored data
1 Trigger before storing data
DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based
on comparator A and B to the CPU upon completion of a tracing session. Please refer to Section 16.4.3,
“Breakpoints,” for further details.
0 CPU break request not enabled
1 CPU break request enabled
Capture Mode Field — See Table 16-4 for capture mode field definitions. In LOOP1 mode, the debugger will
automatically inhibit redundant entries into capture memory. In detail mode, the debugger is storing address and
data for all cycles except program fetch (P) and free (f) cycles. In profile mode, the debugger is returning the
address of the last instruction executed by the CPU on each access of trace buffer address. Refer to
Section 16.4.2.6, “Capture Modes,” for more information.
Table 16-4. CAPMOD Encoding
CAPMOD
00
01
10
11
Description
Normal
LOOP1
DETAIL
PROFILE
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
483