MC9S12KG128_10 Datasheet, PDF(68/606 Page) Freescale Semiconductor, Inc – HCS12 Microcontrollers

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MC9S12KG128_10 Datasheet, PDF (68/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

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Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1)

part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be

secured again.

1.5.3 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block Guide for

information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of

information about the clock system is the Clock and Reset Generator Guide (CRG).

1.5.3.1 Stop

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static

mode. Wake up from this mode can be done via reset or external interrupts.

1.5.3.2 Pseudo Stop

This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running

and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are

turned off. This mode consumes more current than the full STOP mode, but the wake up time from this

mode is signiï¬cantly shorter.

1.5.3.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute

instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay

active. For further power consumption the peripherals can individually turn off their local clocks.

1.5.3.4 Run

Although this is not a low power mode, unused peripheral modules should not be enabled in order to save

power.

1.6 Resets and Interrupts

Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and

interrupts. Both local masking and CCR masking are included as listed in Table 1-12. System resets can

be generated through external control of the RESET pin, through the clock and reset generator module

CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG

and VREG block description chapters for detailed information on reset generation.

1.6.1 Vectors

1.6.1.1 Vector Table

Table 1-12 lists interrupt sources and vectors in default order of priority.

MC9S12KG128 Data Sheet, Rev. 1.16

68

Freescale Semiconductor

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