MC9S12KG128_10 Datasheet, PDF (429/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Timer Module (TIM16B8CV1) Block Description
Field
7
TOI
3
TCRE
Table 13-15. TSCR2 Field Descriptions
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,
TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for
a more detail explanation please refer to Section 13.4.3, “Output Compare
2
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
PR[2:0] Bus Clock as shown in Table 13-16.
Table 13-16. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
13.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
6
5
4
3
2
1
R
C7F
C6F
C5F
C4F
C3F
C2F
C1F
W
Reset
0
0
0
0
0
0
0
Figure 13-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Freescale Semiconductor
MC9S12KG128 Data Sheet, Rev. 1.16
0
C0F
0
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