MC9S12KG128_10 Datasheet, PDF (143/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers. Table 4-2 is a standard memory map of
PIM9KG128.
Table 4-2. PIM9KG128 Memory Map
Address Offset
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006 - 0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
0x001A
0x001B
0x001C
0x001D
0x001E
0x001F
Use
Port T I/O Register (PTT)
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
Port T Polarity Select Register (PPST)
Reserved
Port S I/O Register (PTS)
Port S Input Register (PTIS)
Port S Data Direction Register (DDRS)
Port S Reduced Drive Register (RDRS)
Port S Pull Device Enable Register (PERS)
Port S Polarity Select Register (PPSS)
Port S Wired-OR Mode Register (WOMS)
Reserved
Port M I/O Register (PTM)
Port M Input Register (PTIM)
Port M Data Direction Register (DDRM)
Port M Reduced Drive Register (RDRM)
Port M Pull Device Enable Register (PERM)
Port M Polarity Select Register (PPSM)
Port M Wired-OR Mode Register (WOMM)
Port M Module Routing Register (MODRR)
Port P I/O Register (PTP)
Port P Input Register (PTIP)
Port P Data Direction Register (DDRP)
Port P Reduced Drive Register (RDRP)
Port P Pull Device Enable Register (PERP)
Port P Polarity Select Register (PPSP)
Port P Interrupt Enable Register (PIEP)
Port P Interrupt Flag Register (PIFP)
Access
R/W
R
R/W
R/W
R/W
R/W
—
R/W
R
R/W
R/W
R/W
R/W
R/W
—
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
143