MC9S12KG128_10 Datasheet, PDF (433/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Timer Module (TIM16B8CV1) Block Description
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Table 13-20. Pin Action
Pin Action
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
NOTE
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
CLK1
0
0
1
1
Table 13-21. Timer Clock Selection
CLK0
0
1
0
1
Timer Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer Figure 13-24.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
13.3.2.16 Pulse Accumulator Flag Register (PAFLG)
Module Base + 0x0021
7
6
5
4
3
2
1
R
0
0
0
0
0
0
PAOVF
W
Reset
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 13-25. Pulse Accumulator Flag Register (PAFLG)
0
PAIF
0
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register. Timer module must stay enabled (TEN =1) while clearing thse bits.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
433