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MC9S12KG128_10 Datasheet, PDF (274/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers | |||
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Chapter 9 Freescaleâs Scalable Controller Area Network (S12MSCANV2)
9.1.2 Block Diagram
Oscillator Clock
Bus Clock
MSCAN
CANCLK
Tq Clk
MUX
Presc.
Receive/
Transmit
Engine
RXCAN
TXCAN
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Wake-Up Interrupt Req.
Control
and
Status
Conï¬guration
Registers
Message
Filtering
and
Buffering
Wake-Up
Low Pass Filter
Figure 9-1. MSCAN Block Diagram
9.1.3 Features
The basic features of the MSCAN are as follows:
⢠Implementation of the CAN protocol â Version 2.0A/B
â Standard and extended data frames
â Zero to eight bytes data length
â Programmable bit rate up to 1 Mbps1
â Support for remote frames
⢠Five receive buffers with FIFO storage scheme
⢠Three transmit buffers with internal prioritization using a âlocal priorityâ concept
⢠Flexible maskable identiï¬er ï¬lter supports two full-size (32-bit) extended identiï¬er ï¬lters, or four
16-bit ï¬lters, or eight 8-bit ï¬lters
⢠Programmable wakeup functionality with integrated low-pass ï¬lter
⢠Programmable loopback mode supports self-test operation
⢠Programmable listen-only mode for monitoring of CAN bus
⢠Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
⢠Programmable MSCAN clock source either bus clock or oscillator clock
⢠Internal timer for time-stamping of received and transmitted messages
⢠Three low-power modes: sleep, power down, and MSCAN enable
1. Depending on the actual bit timing and the clock jitter of the PLL.
MC9S12KG128 Data Sheet, Rev. 1.16
274
Freescale Semiconductor
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