MC9S12KG128_10 Datasheet, PDF (122/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 3 2 Kbyte EEPROM Module (S12EETS2KV1)
Module Base + 0x0000
7
6
5
4
3
2
R EDIVLD
W
PRDIV8
EDIV5
EDIV4
EDIV3
EDIV2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-4. EEPROM Clock Divider Register (ECLKDIV)
1
EDIV1
0
0
EDIV0
0
All bits in the ECLKDIV register are readable while bits 6-0 are write once and bit 7 is not writable.
Table 3-3. ECLKDIV Field Descriptions
Field
Description
7
EDIVLD
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
6
PRDIV8
Enable Prescaler by 8
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
5:0
EDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to Section 3.4.1.1, “Writing the
ECLKDIV Register” for more information.
3.3.2.2 RESERVED1
This register is reserved for factory testing and is not accessible to the user.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-5. RESERVED1
All bits read 0 and are not writable.
3.3.2.3 RESERVED2
This register is reserved for factory testing and is not accessible to the user.
MC9S12KG128 Data Sheet, Rev. 1.16
122
Freescale Semiconductor