MC9S12KG128_10 Datasheet, PDF (596/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Appendix A Electrical Characteristics
Table A-23. SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
1 P Operating Frequency
1 P SCK Period
2 D Enable Lead Time
3 D Enable Lag Time
4 D Clock (SCK) High or Low Time
5 D Data Setup Time (Inputs)
6 D Data Hold Time (Inputs)
7 D Slave Access Time
8 D Slave MISO Disable Time
9 D Data Valid (after SCK Edge)
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
12 D Fall Time Inputs and Outputs
f_op
DC
—
t_sck
4
—
t_lead
1
—
t_lag
1
—
t_wsck
t_cyc − 30
—
t_su
25
—
t_hi
25
—
t_a
—
—
t_dis
—
—
t_v
—
—
t_ho
0
—
t_r
—
—
t_f
—
—
Max
1/4
2048
—
—
—
—
—
1
1
25
—
25
25
Unit
f_bus
t_bus
t_cyc
t_cyc
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
A.10 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values
shown on table Table A-24. All major bus signals are included in the diagram. While both a data write and
data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.10.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
MC9S12KG128 Data Sheet, Rev. 1.16
596
Freescale Semiconductor