MC9S12KG128_10 Datasheet, PDF (136/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 3 2 Kbyte EEPROM Module (S12EETS2KV1)
3.5.3 Background Debug Mode
In background debug mode (BDM), the EPROT register is writable. If the chip is unsecured then all
EEPROM commands listed in Table 3-10 can be executed. If the chip is secured in special single-chip
mode, then the only possible command to execute is mass erase.
3.6 Resets
If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted.
The state of the word being programmed or the sector / block being erased is not guaranteed.
3.7 Interrupts
The EEPROM module can generate an interrupt when all EEPROM commands are completed or the
address, data, and command buffers are empty.
Table 3-11. EEPROM Interrupt Sources
Interrupt Source
EEPROM address, data and
command buffers empty
All commands are completed
on EEPROM
Interrupt Flag
CBEIF
(ESTAT register)
CCIF
(ESTAT register)
Local Enable
CBEIE
Global (CCR) Mask
I Bit
CCIE
I Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
For a detailed description of the register bits, refer to Section 3.3.2.4, “EEPROM Configuration Register
(ECNFG)” and Section 3.3.2.6, “EEPROM Status Register (ESTAT)”.
MC9S12KG128 Data Sheet, Rev. 1.16
136
Freescale Semiconductor