MC9S12KG128_10 Datasheet, PDF (439/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Timer Module (TIM16B8CV1) Block Description
13.4.6 Gated Time Accumulation Mode
Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.
The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to
generate interrupt requests.
The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
13.5 Resets
The reset state of each individual bit is listed within Section 13.3, “Memory Map and Register Definition”
which details the registers and their bit fields.
13.6 Interrupts
This section describes interrupts originated by the TIM16B8CV1 block. Table 13-23 lists the interrupts
generated by the TIM16B8CV1 to communicate with the MCU.
Table 13-23. TIM16B8CV1 Interrupts
Interrupt
Offset¹ Vector¹ Priority¹
Source
Description
C[7:0]F
—
—
PAOVI
—
—
PAOVF
—
—
TOF
—
—
1 _{Chip Dependent.}
—
Timer Channel 7–0
Active high timer channel interrupts 7–0
—
Pulse Accumulator Active high pulse accumulator input interrupt
Input
—
Pulse Accumulator
Overflow
Pulse accumulator overflow interrupt
—
Timer Overflow
Timer Overflow interrupt
The TIM16B8CV1 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
13.6.1 Channel [7:0] Interrupt (C[7:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be
serviced by the system controller.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
439