MC9S12KG128_10 Datasheet, PDF (186/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4) Block Description
5.3.2.6 CRG Clock Select Register (CLKSEL)
This register controls CRG clock selection. Refer to Figure 5-17 for details on the effect of each bit.
Module Base + 0x0005
R
W
Reset
7
PLLSEL
0
6
PSTP
5
SYSWAI
4
ROAWAI
3
PLLWAI
2
CWAI
0
0
0
0
0
Figure 5-9. CRG Clock Select Register (CLKSEL)
Read: anytime
Write: refer to each bit for individual write conditions
Table 5-4. CLKSEL Field Descriptions
1
RTIWAI
0
0
COPWAI
0
Field
7
PLLSEL
6
PSTP
5
SYSWAI
4
ROAWAI
3
PLLWAI
Description
PLL Select Bit — Write anytime. Writing a 1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has
no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU
enters self-clock mode, stop mode or wait mode with PLLWAI bit set.
0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2).
1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2).
Pseudo-Stop Bit — Write: anytime — This bit controls the functionality of the oscillator during stop mode.
0 Oscillator is disabled in stop mode.
1 Oscillator continues to run in stop mode (pseudo-stop). The oscillator amplitude is reduced. Refer to oscillator
block description for availability of a reduced oscillator amplitude.
Note: Pseudo-stop allows for faster stop recovery and reduces the mechanical stress and aging of the resonator
in case of frequent stop conditions at the expense of a slightly increased power consumption.
Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any
electro-magnetic susceptibility (EMS) tests.
System Clocks Stop in Wait Mode Bit — Write: anytime
0 In wait mode, the system clocks continue to run.
1 In wait mode, the system clocks stop.
Note: RTI and COP are not affected by SYSWAI bit.
Reduced Oscillator Amplitude in Wait Mode Bit — Write: anytime — Refer to oscillator block description
chapter for availability of a reduced oscillator amplitude. If no such feature exists in the oscillator block then
setting this bit to 1 will not have any effect on power consumption.
0 Normal oscillator amplitude in wait mode.
1 Reduced oscillator amplitude in wait mode.
Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any
electro-magnetic susceptibility (EMS) tests.
PLL Stops in Wait Mode Bit — Write: anytime — If PLLWAI is set, the CRGV4 will clear the PLLSEL bit before
entering wait mode. The PLLON bit remains set during wait mode but the PLL is powered down. Upon exiting
wait mode, the PLLSEL bit has to be set manually if PLL clock is required.
While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected
target frequency after exiting wait mode.
0 PLL keeps running in wait mode.
1 PLL stops in wait mode.
MC9S12KG128 Data Sheet, Rev. 1.16
186
Freescale Semiconductor