MC9S12KG128_10 Datasheet, PDF (104/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
Data Compress Operation
The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature
based on selected Flash array data. The final signature, which is stored in the FDATA register, is based on
the following logic equation which is executed on every data compression cycle during the operation:
MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0]
Eqn. 2-1
where MISR is the content of the internal signature register and DATA is the data to be compressed as
shown in Figure 2-26.
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[15]
+ DQ + DQ + DQ + DQ + DQ + DQ
...
M0
M1
M2
M3
M4
M5
>
>
>
>
>
>
+ DQ
M15
>
+
+ = Exclusive-OR
MISR[15:0] = Q[15:0]
+
+
Figure 2-26. 16-Bit MISR Diagram
During the data compress operation, the following steps are executed:
1. MISR is reset to 0xFFFF.
2. DATA from the selected Flash array data range is read and compressed into the MISR with address
incrementing.
3. DATA from the selected Flash array data range is read and compressed into the MISR with address
decrementing.
4. The contents of the MISR are written to the FDATA register.
MC9S12KG128 Data Sheet, Rev. 1.16
104
Freescale Semiconductor