MC9S12KG128_10 Datasheet, PDF (92/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
FADDRHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-13. Flash Address High Register (FADDRHI)
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
FADDRLO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-14. Flash Address Low Register (FADDRLO)
All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a
command write sequence, the FADDR registers will contain the mapped MCU address written. If a double
bit fault is detected, as indicated by the setting of the DFDIF bit in the FSTAT register, the faulty Flash
block address is stored in the FADDR registers as a word address. The faulty Flash block address remains
readable until the start of the next command write sequence. The mapping of the FADDR registers to the
MCU address is shown in Figure 2-15 and Figure 2-16.
MCU Address
Byte Select
1 0 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
PPAGE Register
1 1 1 PIX2 PIX1 PIX0
FADDR Register
FADDRHI[7:0]
FADDRLO[7:0]
Figure 2-15. FADDR to MCU Address Mapping (Paged)
MC9S12KG128 Data Sheet, Rev. 1.16
92
Freescale Semiconductor