MC9S12KG128_10 Datasheet, PDF (166/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.5.7 Port H Interrupt Enable Register (PIEH)
Module Base + 0x0026
7
R
PIEH7
W
6
PIEH6
5
PIEH5
4
PIEH4
3
PIEH3
2
PIEH2
1
PIEH1
0
PIEH0
Reset
0
0
0
0
0
0
0
0
Figure 4-37. Port H Interrupt Enable Register (PIEH)
Read: Anytime. Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port H.
Table 4-34. PIEH Field Descriptions
Field
Description
7–0
PIEH[7:0]
Interrupt Enable Port H
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
4.3.5.8 Port H Interrupt Flag Register (PIFH)
Module Base + 0x0027
7
R
PIFH7
W
6
PIFH6
5
PIFH5
4
PIFH4
3
PIFH3
2
PIFH2
1
PIFH1
0
PIFH0
Reset
0
0
0
0
0
0
0
0
Figure 4-38. Port H Interrupt Flag Register (PIFH)
Read: Anytime. Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSH register. To clear this flag, write “1” to the corresponding bit in the PIFH register.
Writing a “0” has no effect.
Table 4-35. PIFH Field Descriptions
Field
Description
7–0
PIFH[7:0]
Interrupt Flags Port H
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
MC9S12KG128 Data Sheet, Rev. 1.16
166
Freescale Semiconductor