MC9S12KG128_10 Datasheet, PDF (552/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 19 Module Mapping Control (MMCV4) Block Description
19.3.2.4 Miscellaneous System Control Register (MISC)
Module Base + 0x0013
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
R
0
0
0
0
EXSTR1 EXSTR0
W
Reset: Expanded
or Emulation
0
0
0
0
1
1
Reset: Peripheral
or Single Chip
0
0
0
0
1
1
Reset: Special Test
0
0
0
0
1
1
1. The reset state of this bit is determined at the chip integration level.
= Unimplemented or Reserved
Figure 19-6. Miscellaneous System Control Register (MISC)
1
ROMHM
0
0
0
0
ROMON
—¹
1
0
Read: Anytime
Write: As stated in each bit description
NOTE
Writes to this register take one cycle to go into effect.
This register initializes miscellaneous control functions.
Table 19-5. INITEE Field Descriptions
Field
Description
3:2
EXSTR[1:0]
External Access Stretch Bits 1 and 0
Write: once in normal and emulation modes and anytime in special modes
This two-bit field determines the amount of clock stretch on accesses to the external address space as shown in
Table 19-6. In single chip and peripheral modes these bits have no meaning or effect.
1
ROMHM
FLASH EEPROM or ROM Only in Second Half of Memory Map
Write: once in normal and emulation modes and anytime in special modes
0 The fixed page(s) of FLASH EEPROM or ROM in the lower half of the memory map can be accessed.
1 Disables direct access to the FLASH EEPROM or ROM in the lower half of the memory map. These physical
locations of the FLASH EEPROM or ROM remain accessible through the program page window.
0
ROMON
ROMON — Enable FLASH EEPROM or ROM
Write: once in normal and emulation modes and anytime in special modes
This bit is used to enable the FLASH EEPROM or ROM memory in the memory map.
0 Disables the FLASH EEPROM or ROM from the memory map.
1 Enables the FLASH EEPROM or ROM in the memory map.
MC9S12KG128 Data Sheet, Rev. 1.16
552
Freescale Semiconductor