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MC9S12KG128_10 Datasheet, PDF (89/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers | |||
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Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
CCIF
BLANK
0
CBEIF
PVIOL
ACCERR
DFDIF
FAIL
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-10. Flash Status Register (FSTAT - Special Mode)
CBEIF, PVIOL, ACCERR and DFDIF are readable and writable, CCIF and BLANK are readable and not
writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in
special mode. FAIL must be clear when starting a command write sequence.
Table 2-16. FSTAT Field Descriptions
Field
Description
7
CBEIF
Command Buffer Empty Interrupt Flag â The CBEIF ï¬ag indicates that the address, data and command
buffers are empty so that a new command write sequence can be started. The CBEIF ï¬ag is cleared by writing
a 1 to CBEIF. Writing a 0 to the CBEIF ï¬ag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned
word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause
the ACCERR ï¬ag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR
ï¬ag. The CBEIF ï¬ag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request
(see Figure 2-31).
0 Buffers are full.
1 Buffers are ready to accept a new command.
6
CCIF
Command Complete Interrupt Flag â The CCIF ï¬ag indicates that there are no more commands pending. The
CCIF ï¬ag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending
commands. The CCIF ï¬ag does not set when an active commands completes and a pending command is
fetched from the command buffer. Writing to the CCIF ï¬ag has no effect on CCIF. The CCIF ï¬ag is used together
with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 2-31).
0 Command in progress.
1 All commands are completed.
5
PVIOL
Protection Violation Flag â The PVIOL ï¬ag indicates an attempt was made to program or erase an address
in a protected area of the Flash block during a command write sequence. The PVIOL ï¬ag is cleared by writing a
1 to PVIOL. Writing a 0 to the PVIOL ï¬ag has no effect on PVIOL. While PVIOL is set, it is not possible to launch
a command or start a command write sequence.
0 No failure.
1 A protection violation has occurred.
4
ACCERR
Access Error Flag â The ACCERR ï¬ag indicates an illegal access to the Flash array caused by either a
violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in
the FCMD register), launching the sector erase abort command terminating a sector erase operation early,
detection of a double fault or the execution of a CPU STOP instruction while a command is executing (CCIF =
0). The ACCERR ï¬ag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR ï¬ag has no effect on
ACCERR. While ACCERR is set, it is not possible to launch a command or start a command write sequence. If
ACCERR is set by the detection of a double fault, an erase verify operation or a data compress operation, any
buffered command will not launch.
0 No access error detected.
1 Access error has occurred.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
89
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