MC9S12KG128_10 Datasheet, PDF (510/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 17 Interrupt (INTV1) Block Description
Table 17-2. ITCR Field Descriptions
Field
Description
4
WRTINT
3:0
ADR[3:0]
Write to the Interrupt Test Registers
Read: anytime
Write: only in special modes and with I-bit mask and X-bit mask set.
0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs.
1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers
instead.
Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten.
Test Register Select Bits
Read: anytime
Write: anytime
These bits determine which test register is selected on a read or write. The hexadecimal value written here will
be the same as the upper nibble of the lower byte of the vector selects. That is, an “F” written into ADR[3:0] will
select vectors 0xFFFE–0xFFF0 while a “7” written to ADR[3:0] will select vectors 0xFF7E–0xFF70.
17.3.2.2 Interrupt Test Registers
Module Base + 0x0016
Starting address location affected by INITRG register setting.
R
W
Reset
7
INTE
0
6
INTC
5
INTA
4
INT8
3
INT6
2
INT4
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-3. Interrupt TEST Registers (ITEST)
1
INT2
0
0
INT0
0
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt
sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always
return 0s in normal modes.
Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
MC9S12KG128 Data Sheet, Rev. 1.16
510
Freescale Semiconductor