MC9S12KG128_10 Datasheet, PDF (512/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 17 Interrupt (INTV1) Block Description
17.4.1 Low-Power Modes
The INT does not contain any user-controlled options for reducing power consumption. The operation of
the INT in low-power modes is discussed in the following subsections.
17.4.1.1 Operation in Run Mode
The INT does not contain any options for reducing power in run mode.
17.4.1.2 Operation in Wait Mode
Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be
used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
17.4.1.3 Operation in Stop Mode
Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be
used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
17.5 Resets
The INT supports three system reset exception request types: normal system reset or power-on-reset
request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request
must be decoded by the system and the proper request made to the core. The INT will then provide the
service routine address for the type of reset requested.
17.6 Interrupts
As shown in the block diagram in Figure 17-1, the INT contains a register block to provide interrupt status
and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate
whether pending interrupts are valid and assess their priority.
17.6.1 Interrupt Registers
The INT registers are accessible only in special modes of operation and function as described in
Section 17.3.2.1, “Interrupt Test Control Register,” and Section 17.3.2.2, “Interrupt Test Registers,”
previously.
17.6.2 Highest Priority I-Bit Maskable Interrupt
When the optional HPRIO block is implemented, the user is allowed to promote a single I-bit maskable
interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and
passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces
the promoted interrupt source.
MC9S12KG128 Data Sheet, Rev. 1.16
512
Freescale Semiconductor