MC9S12KG128_10 Datasheet, PDF (296/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (S12MSCANV2)
9.3.2.16 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 9.3.3.1,
“Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 9.4.3,
“Identifier Acceptance Filter”).
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 (CANIDAR0)
0x0011 (CANIDAR1)
0x0012 (CANIDAR2)
0x0013 (CANIDAR3)
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 9-19. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Field
7:0
AC[7:0]
Table 9-19. CANIDAR0–CANIDAR3 Register Field Descriptions
Description
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
MC9S12KG128 Data Sheet, Rev. 1.16
296
Freescale Semiconductor