MC9S12KG128_10 Datasheet, PDF (589/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Appendix A Electrical Characteristics
A.7.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.7.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp
VDDPLL
Cs
R
XFC Pin
Phase
VCO
fosc
1
fref
refdv+1
D
KF
fvco
KV
Detector
fcmp
Loop Divider
1
1
synr+1
2
Figure A-3. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K₁, f₁ and i_ch from Table A-20.
The grey boxes show the calculation for f_VCO = 50MHz and f_ref = 1MHz. E.g., these frequencies are used
for f_OSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
KV = K1 ⋅ e-^{(--f--K1----1-–----⋅f--v-1--c-V---o----)}
The phase detector relationship is given by:
= –100 ⋅ e^{(---6---–0---1-–--0---50---0---)-} = -90.48MHz/V
K_Φ = – ich ⋅ KV _{= 316.7Hz/Ω}
i_ch is the current in tracking mode.
The loop bandwidth f_C should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
589