MC9S12KG128_10 Datasheet, PDF (337/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Field
1
RWU
0
SBK
Chapter 10 Serial Communications Interface (S12SCIV2) Block Description
Table 10-4. SCICR2 Field Descriptions (continued)
Description
Receiver Wakeup Bit — Standby state
0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes
the receiver by automatically clearing RWU.
Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s
if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As
long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13
or 14 bits).
0 No break characters
1 Transmit break characters
10.3.2.4 SCI Status Register 1 (SCISR1)
The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also,
these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures
require that the status register be read followed by a read or write to the SCI Data Register.It is permissible
to execute other instructions between the two steps as long as it does not compromise the handling of I/O,
but the order of operations is important for flag clearing.
Module Base + 0x_0004
7
6
5
4
3
2
1
0
R TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-6. SCI Status Register 1 (SCISR1)
Read: Anytime
Write: Has no meaning or effect
Table 10-5. SCISR1 Field Descriptions
Field
7
TDRE
6
TC
Description
Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the
SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value
to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data
register low (SCIDRL).
0 No byte transferred to transmit shift register
1 Byte transferred to transmit shift register; transmit data register empty
Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break
character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being
transmitted.When TC is set, the TXD out signal becomes idle (logic 1). Clear TC by reading SCI status register
1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when
data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and
clear of the TC flag (transmission not complete).
0 Transmission in progress
1 No transmission in progress
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
337