MC9S12KG128_10 Datasheet, PDF (153/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.3.3 Port M Data Direction Register (DDRM)
Module Base + 0x0012
7
R
DDRM7
W
6
DDRM6
5
DDRM5
4
DDRM4
3
DDRM3
2
DDRM2
1
DDRM1
0
DDRM0
Reset
0
0
0
0
0
0
0
0
Figure 4-17. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime.
This register configures each port M pin as either input or output. The CAN forces the I/O state to be an
output for each port line associated with an enabled output (TXCAN4 and TXCAN0). It also forces the
I/O state to be an input for each port line associated with an enabled input (RXCAN4 and RXCAN0). In
those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction
of a pin when the associated peripheral module is disabled.
Table 4-12. DDRM Field Descriptions
Field
7–0
Data Direction Port M
DDRM[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
4.3.3.4 Port M Reduced Drive Register (RDRM)
Module Base + 0x0013
R
W
Reset
7
RDRM7
0
6
RDRM6
0
5
RDRM5
0
4
RDRM4
0
3
RDRM3
0
2
RDRM2
0
1
RDRM1
0
0
RDRM0
0
Figure 4-18. Port M Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime.
This register configures the drive strength of each port M output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 4-13. RDRM Field Descriptions
Field
Description
7–0
Reduced Drive Port M
RDRM[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
153