MC9S12KG128_10 Datasheet, PDF (537/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.16 Port K Data Direction Register (DDRK)
Module Base + 0x0033
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 18-20. Port K Data Direction Register (DDRK)
Read: Anytime
Write: Anytime
This register determines the primary direction for each port K pin configured as general-purpose I/O. This
register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is
set. Therefore, these accesses will be echoed externally.
Table 18-14. EBICTL Field Descriptions
Field
7:0
DDRK
Description
Data Direction Port K Bits
0 Associated pin is a high-impedance input
1 Associated pin is an output
Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to
outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling
as outputs.
Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing
to the DDRK register before reading from the PORTK register.
18.4 Functional Description
18.4.1 Detecting Access Type from External Signals
The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses
to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because
the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these
cases the data for the address that was accessed is on the low half of the data bus and the data for
address + 1 is on the high half of the data bus. This is summarized in Table 18-15.
Table 18-15. Access Type vs. Bus Control Pins
LSTRB
1
0
1
0
AB0
0
1
0
1
R/W
Type of Access
1
8-bit read of an even address
1
8-bit read of an odd address
0
8-bit write of an even address
0
8-bit write of an odd address
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
537