MC9S12KG128_10 Datasheet, PDF (90/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
Table 2-16. FSTAT Field Descriptions
Field
3
DFDIF
2
BLANK
1
FAIL
Description
Double Fault Detect Interrupt Flag — The DFDIF flag indicates that one of the following Flash block operations
has detected a double bit fault in the stored parity and data bits.
• Array Read.
• Erase Verify.
• Data Compress.
• Reset Sequence (reads of the protection and security fields stored in the Flash memory).
When the DFDIF flag is set during a Flash array read operation, the data read from the Flash module are the
data bits read out of the Flash array without correction and should be considered invalid. When the DFDIF flag
is set during a Flash array read, erase verify, data compress or reset sequence operation, the Flash block
address containing the parity and data bits that caused the DFDIF flag to set will be stored in the FADDR register
and the parity bits will be stored in the FDATA register. The DFDIF flag is cleared by writing a 1 to the ACCERR
bit which is set when the DFDIF flag is set. Writing a 0 to the DFDIF flag has no effect on DFDIF. The DFDIF flag
is used together with the DFDIE enable bit to generate an interrupt request (see Figure 2-31). While DFDIF is
set, Flash array read operations are allowed. If DFDIF is not cleared and another double bit fault is detected, the
FADDR and FDATA registers will maintain the contents from the fault that caused the DFDIF bit to set.
0 No double bit fault detected.
1 Double bit fault detected.
Erase Verify Operation Status Flag — When the CCIF flag is set after completion of an erase verify command,
the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module
when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect
on BLANK.
0 Flash block verified as not erased.
1 Flash block verified as erased.
Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (Flash block
verified as not erased). The FAIL flag will also set if a double bit fault is detected during an array read, erase
verify, or data compress operation. The FAIL flag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL flag
has no effect on FAIL.
0 Flash operation completed without error.
1 Flash operation failed.
2.3.2.8 Flash Command Register (FCMD)
The FCMD register is the Flash command register.
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
0
W
CMDB
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-11. Flash Command Register (FCMD - NVM User Mode)
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
MC9S12KG128 Data Sheet, Rev. 1.16
90
Freescale Semiconductor