MC9S12KG128_10 Datasheet, PDF (200/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4) Block Description
running at minimum operating frequency; this mode of operation is called self-clock mode. This requires
CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the
PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically
select OSCCLK to be the system clock and return to normal mode. See Section 5.4.4, “Clock Quality
Checker” for more information on entering and leaving self-clock mode.
NOTE
In order to detect a potential clock loss, the CME bit should be always
enabled (CME=1).
If CME bit is disabled and the MCU is configured to run on PLL clock
(PLLCLK), a loss of external clock (OSCCLK) will not be detected and will
cause the system clock to drift towards the VCO’s minimum frequency
f_SCM. As soon as the external clock is available again the system clock
ramps up to its PLL target frequency. If the MCU is running on external
clock any loss of clock will cause the system to go static.
5.4.8 Low-Power Operation in Run Mode
The RTI can be stopped by setting the associated rate select bits to 0.
The COP can be stopped by setting the associated rate select bits to 0.
5.4.9 Low-Power Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during wait mode.
Table 5-10 lists the individual configuration bits and the parts of the MCU that are affected in wait mode.
Table 5-10. MCU Configuration During Wait Mode
PLLWAI CWAI SYSWAI RTIWAI COPWAI ROAWAI
PLL
stopped
—
—
—
—
—
Core
—
stopped stopped
—
—
—
System
—
—
stopped
—
—
—
RTI
—
—
—
stopped
—
—
COP
—
—
—
—
stopped
—
Oscillator
—
—
—
—
—
reduced¹
1 _{Refer to oscillator block description for availability of a reduced oscillator amplitude.}
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG
then checks whether the PLLWAI, CWAI and SYSWAI bits are asserted (see Figure 5-23). Depending on
the configuration the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit,
disables the PLL, disables the core clocks and finally disables the remaining system clocks. As soon as all
clocks are switched off wait mode is active.
MC9S12KG128 Data Sheet, Rev. 1.16
200
Freescale Semiconductor